A Voltage-and-digitally Controlled Oscillator with High Efficiency for a Multi-standard Hybrid PLL

This paper presents a high efficiency voltage-and-digitally controlled oscillator (VDCO) for a multi-standard hybrid PLL. It adopts a fixed-bias class-B topology and high-speed dithering technique that saves power consumption for the same phase noise performance. The proposed VDCO is a dual controllable oscillator which can be driven simultaneously by an analog voltage and a digital word. It operates from 3 GHz to 4.9 GHz, covering bands of GSM/EDGE and LTE. In the GSM/EDGE mode, the VDCO behaves as a phase modulator which has a 0.9 degree root-mean-square (RMS) phase error and EVM of 2.87% with power consumption of 19.5 mW. In the LTE mode, the VDCO operates just as a voltage-controlled oscillator (VCO) which has an RMS jitter of 350 fs with power consumption of 12 mW. The resulting figure-of-merit of the proposed VDCO is 183.8 dBc/Hz, which is superior to recent multi-standard oscillators. This VDCO is implemented in a 65-nm CMOS technology and occupies 0.16 mm(2)