Impact of Device Aging on Early Mode Failures in Pulsed Latches

Pulsed latches that are widely used in high performance circuits are susceptible to early mode failures. High performance circuits also experience higher voltage and temperature conditions that exacerbates device degradation due to mechanisms such as BTI and HCI. In this paper, the impact of aging on hold slack in pulsed latches is presented. Analysis of clock gating that leads to AC or DC stress in the pulse generation circuits is illustrated, and the need to provide additional hold margin for these effects is demonstrated.