A time interleaved, 10 bit SAR ADC with split capacitor DAC for diffraction imaging at X-ray FELs

The PixFEL project aims at substantially advancing the state of the art in the field of 2D X-ray imaging for application at the next generation free electron laser (FEL) facilities. The collaboration intends to take advantage of cutting-edge microelectronic technologies and innovative design and architectural solutions, to build a large area focal plane detector based on an active edge sensor interconnected to a dual layer front-end chip with on board memory. For this purpose, the groups participating in the project are developing the fundamental building blocks for the detector, including slim edge sensors, a low noise analog front-end with dynamic compression feature and a high resolution and low power ADC. This work focuses on the design and characterization of the ADC. An interleaved SAR ADC architecture was adopted to obtain a good trade-off between power, conversion speed and area occupation. The design has been carried out in a 65 nm CMOS technology. Different test structures have been designed and tested as stand-alone circuits, with an area going from 0.00563 mm ² to 0.0072 mm ² . The maximum DNL and INL obtained from the most promising structure are 1 LSB and 4.4 LSB, respectively. The input noise is around 0.4 LSB. From simulation, the power consumption is 85 μW. An improved ADC version has been included in a recently designed test chip, including an array of 32×32 pixels.