3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS

Delong Cui,Heng Zhang,Nick Huang,Ali Nazemi,Burak Çatli,Hyo-Gyuem Rhew,Bo Zhang,Afshin Momtaz,Jun Cao

2016 IEEE International Solid-State Circuits Conference (ISSCC)（2016）

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摘要

Multilevel modulation formats, such as PAM-4, have been introduced in recent years for next generation wireline communication systems for more efficient use of the available link bandwidth. High-speed ADCs with digital signal processing (DSP) can provide robust performance for such systems to compensate for the severe channel impairment as the data rate continues to increase.

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关键词

DSP,digital signal processing,high-speed ADC,next generation wireline communication systems,multilevel modulation,CMOS,analog peaking,programmable gain control,PAM-4 analog front-end,current 3.2 A,power 320 mW,bit rate 32 Gbit/s,size 28 nm

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