Comparative Performance Analysis of Nanometer Scale Double Gate MOSFETs

The field effect transistor fabricated in integrated circuits are majorly with junctions. Due to the device scaling, the fabrication of these junctions have become gradually more difficult. Also there is stringent necessity for having high doping concentration gradient for smooth functioning of the device. Recently, researchers are focusing on new devices where devices are junction less and no doping gradient requirement. One such structure is the Double Gate MOSFET (DG-MOSFET) which have shown improved performance against short channel effect, namely drain induced barrier lowering (DIBL), changes in threshold Voltage etc. The work in the paper considers a physical 2-D model of threshold voltage to study DGMOSFET. The model helps to investigate how threshold voltage degrade due to MOSFET parameters namely, silicon channel layer thickness, silicon dioxide (SiO2) layer thickness, drain bias and effective gate channel length.