Overcoming The Reliability Limitation In The Ultimately Scaled Dram Using Silicon Migration Technique By Hydrogen Annealing

We demonstrated a highly reliable buried-gate saddle-fin cell-transistor (cell-TR) using silicon migration technique of hydrogen (H-2) annealing after a dry etch to form the saddle-fin in a fully integrated 2y-nm 4Gb DRAM. It clearly shows a reduction in interface trap density with highly enhanced variable-retention-time (VRT) and Row-Hammering immunity.