Optimization Design For A Cds Circuit With Offset Canceling

Correlated double sampling(CDS) operation is generally used in CMOS imaging systems, implemented by switched capacitor(SC) circuits, to get rid of reset noise and decrease flicker noise. This paper presents an optimization method for the noise performance of a CDS circuit, the advantage of which is its ability of canceling the offset of the OP involved. The structure of the CDS circuit is analyzed with operation timing at first. Then the noise model of each individual clock phase is established based on the transient noise behavior, from which we derive the expressions of each independent noise source contributing to the whole output noise power. Using the expressions we can optimize the design of crucial capacitors of the circuit.