Efficient integrated bus coding scheme for low-power I/O

Bus-Invert (BI) coding schemes have been used in the circuit design to save power usage by minimizing the number of transitions between successive words. With an increased number of bits for bus width, many other coding schemes like Bus-Shift (BS) and Shift-Invert (SINV) have been proposed for better power saving. In this paper, we are proposing a new Successive Shift-Invert (SSINV) coding scheme where the transmitting data will first be inverted. Then both the original and the inverted word will be shifted circularly for each bit and compared with the data just sent for least hamming distance. Thus, the combination having the least hamming distance with the last sent data will be selected and sent. The proposed method exhibits better power saving compared to other reported methods, but needs one extra control bit than BS; which add to the computation time. Simulation results show a saving margin of 5–15% in average cases in comparison with BI, BS, and SINV for higher bus width. A VerilogA implementation of SSINV using TSMC 65nm technology is also presented as a proof of concept.