Circuit relevant HCS lifetime assessments at single transistors with emulated variable loads

Hot carrier induced degradation of MOSFETs is still a concern for circuit reliability and not yet fully understood [1-4]. On the one hand stress measurements at single devices reveal critical parameter degradation for modern technologies especially at high VD=VG. On the other hand there are several publications stating that at least for combinational logic HCS plays only minor role for lifetime limits [e.g. 5]. In 2010 we have published experimental data of an integrated aging monitor demonstrating the small HCS impact on the lifetime of a critical logic path [6]. This discrepancy needs further investigation. An accurate circuit relevant assessment method is required to evaluate the correct HCS impact on lifetime. In this paper we introduce a new methodology to investigate and qualify product relevant HCS lifetime at single test devices with waveform AC-stress. We investigate the proportion of occurring device degradation mechanisms during digital circuit operations and clarify the different impact factors. Finally we compare the results of the new set-up in detail with the standard worst case approach based on experimental data in 130nm and 40nm technology nodes.