Harmonic-free and low cost delay-locked loop with a 20%~80% input duty cycle

A low-cost two-step delay locked loop (DLL) with a 20-80% input duty cycle is presented. For eliminating harmonic and zero-trap locking issues along the whole range of digital controlled delay line, a hierarchy phase detector (HPD) is proposed to compare the phase difference between input reference clock and two phase-isotonic clocks generated by sharing a common delay line. By monitoring of HPD's...