An Improved Frequency Compensation Techinique For Low Power,Low Voltage Cmos Amplifiers

This paper presents an improved frequency compensation technique for low power and low voltage CMOS operational amplifier. The Op Amp designed for a high speed high resolution pipeline ADC is a two-stage with folded-cascode as the first stage and uses this improved compensation technique to achieve closed loop bandwidth of 350MHz while driving a 2K resistor load and a 3.5pF capacitive load consuming much lower power when compared to the conventional miller compensation technique or cascode compensation technique. The Op Amp was designed in a 0.15-mum CMOS technology and achieves a THD of 70dB for a 30MHz signal and consumes a total power of 4mW of a 1.35V supply.