A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications

2016 IEEE 8th International Memory Workshop (IMW)(2016)

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摘要
For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications . The write and read bandwidth is equal to 533MB/s, and the random read latency is 37.5ns, while the write latency is 11.25ns supporting a random write cycle of 176.7ns. In addition, a record high switching speed of 128ns with good resistance distribution is demonstrated with a super-fast Set material.
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关键词
double-data-rate 2,DDR2 interface phase-change memory,PCM,read-write data rate,access latency,memory-type storage class memory applications,M-type storage class memory applications,multiple individual bank sensing-writing,memory bank interleave design,DRAM,random read latency,write latency,random write cycle,SETmaterial
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