A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process

Chia Hsin Lee, Chih Huei Hou,Chun Po Huang,Soon-Jyh Chang,Yuan Ta Hsieh,Ying Zong Juang

2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)（2016）

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摘要

This paper presents a single-channel 2.5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with conventional 2.5-bit/cycle SAR ADC, the proposed technique can save one sub-digital-to-analog converter (sub-DAC) and reduce the requirement on resolution for the other sub-DACs. Besides, the proposed digital code error correction provides a wider error tolerance range. The proposed ADC was fabricated in TSMC 90-nm CMOS process. At 1-V supply and 160 MS/s, the measured peak signal-to-noise and distortion ratio (SNDR) is 53.06 dB with power consumption of 1.97 mW.

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关键词

SAR ADC,CMOS process,successive approximation register,analog-to-digital converter,subdigital-to-analog converter,sub-DAC,digital code error correction,error tolerance,TSMC,signal-to-noise and distortion ratio,SNDR,power consumption,complementary metal oxide semiconductor,word length 10 bit,size 90 nm,voltage 1 V,power 1.97 mW

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