Mini-computer PDP-8 ISA Simulator Design and Verification

This paper introduces a simple instruction set architecture simulator for the PDP-8 mini-computer. It generates a memory trace file from an assembled input object file. The memory trace file indicates whether the access was an instruction fetch, data read or data write. The simulator supports all instructions except for input/output and group 3 microinstructions. A summary of the total number of instructions executed, clock cycles consumed and instruction count by mnemonic is outputted at the end of simulation. A branch trace file is generated listing instruction branches by program counter, branch type, target address and whether taken or not.