BJT Device and Circuit Co-Optimization Enabling Bandgap Reference and Temperature Sensing in 7-nm FinFET

2018 48th European Solid-State Device Research Conference (ESSDERC)(2018)

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摘要
Caused by the increased power density and strong thermal gradients in today's large SoC/FPGAs in scaled process technologies, high-precision bandgap references and temperature sensors have become some of the most critical analog blocks. BJT devices form core components of such benchmark analog circuitry, thanks to their linear dependence on temperature. This paper discusses BJT device modeling and characterization results in 7-nm FinFET CMOS technology with regard to the BJT's variability and process spread. It provides guidance useful for the circuit implementation and quantifies the circuit application performance. Two test-chip device arrays are presented to demonstrate the feasibility of using BJTs in FinFET CMOS. A bandgap reference circuit is designed using the developed SPICE model. It shows measured max inaccuracy of +/- 0.2%. The presented merged layout structure further saves 20% of area.
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关键词
merged layout structure,SPICE model,BJT device modeling,circuit co-optimization,BJT variability,SoC-FPGA,thermal gradients,power density,FinFET CMOS technology,core components,critical analog blocks,temperature sensors,high-precision bandgap references,scaled process technologies,temperature sensing,bandgap reference circuit,test-chip device arrays,circuit application performance,circuit implementation,benchmark analog circuitry,size 7 nm
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