A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS.

X. Shawn Wang,Xin Jin,Jieqiong Du,Yilei Li,Yuan Du,Chien-Heng Wong,Yen-Cheng Kuan,Chi-Hang Chan,Mau-Chung Frank Chang

IEEE Transactions on Circuits and Systems II: Express Briefs（2018）

引用 6|浏览25

暂无评分

摘要

This brief presents a two-way time-interleaved two-step pipelined analog-to-digital converter (ADC) architecture built upon a new concept of virtual-ground sampling, featuring merged front-end track-and-hold, residue generation, input termination, and buffering. This architecture is investigated to alleviate the front-end performance tradeoff among the total-harmonic-distortion, bandwidth, and sam...

查看译文

关键词

Switches,Linearity,Clocks,Timing,Bandwidth,Distortion,Signal resolution

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要