A 19Gb/s RX for VSR-C2C Links with Clock-Less DFE and High-BW CDR Based on Master-Slave ILOs in 14nm CMOS.

Proceedings of the European Solid-State Circuits Conference（2018）

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摘要

A receiver with a reference-less clocking architecture for high-density VSR-C2C links is described. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The receiver is implemented in 14nm CMOS and characterized at 19Gb/s. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER< 10(-12)) across a 15dB loss channel. The jitter tolerance BW of the receiver is 250MHz and the INL of the ILO-based phase-rotator (32(Step/U1)) is <1-LSB.

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关键词

clockless DFE,high-bandwidth CDR,master-slave ILOs,jitter tolerance BW,ILO-based phase-rotator,high-BW CDR,high-density VSR-C2C links,CMOS,phase generation-rotation,very short reach copper interconnects,chip-to-chip communication,size 14.0 nm,frequency 250.0 MHz,bit rate 19 Gbit/s,loss 15 dB

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