A Low-Cost Soft Error Tolerant Read Circuit for Single/Multi-Level Cross-Point RRAM Arrays

Although RRAM as an emerging non-volatile memory has solved many dr awbacks of conventional memor ies, it has deficiencies needed to be maintained. The objective of this paper is to suppress the soft er ror susceptibility of CMOSbased peripheral read circuits for both SLC and MLC crosspoint RRAM arrays thr ough sizing of tr ansistor s with regard to area, power, and delay constr aints. The results revealed that the soft err or r ate (SER) has improved around 18.4 and 53.7 times mor e than the default sizing in case of fully-robust sizing besides minor area overhead for both SLC and MLC RRAM ar r ays, respectively. However, the static power and delay of MLC ar r ay are the overheads.