Extending universal verification methodology with fault injection capabilities

Embedded Systems verification has become a major challenge in recent years due to the increased hardware and software complexity and to the shorter time to market. In order to overcome these issues, new verification methodologies and fault injection techniques are strongly recommended to increase safety quality of complex systems. In this paper, we propose an integration methodology to extend the Universal Verification Methodology (UVM) with fault injection capabilities. For that, we extend the UVM components and use the UVM's data share resources to manipulate data. We have successfully applied this optimized hybrid fault-verification methodology to the algorithms: Advanced Encryption Standard (AES) and Cyclic Redundancy Check (CRC). Memory failures were simulated in a virtual platform developed for MSP430 microcontroller Instruction Set Simulator (ISS) and a TLM memory model. The results show that our approach scales to increase the system's dependability validation creating reusable Testbenches with fault injection test in UVM.