A 3 mW 1.2-3.6 GHz Multi-Phase PLL-Based Clock Generator with TDC Assisted Auto-Calibration of Loop Bandwidth.

A PLL-based clock generator with an auto-calibration circuit is presented. The auto-calibration circuit employs an oscillator-based time-to-digital converter (TDC) to achieve a constant loop bandwidth and fast lock time. The TDC measures the operating frequency of M-stage ring-VCO with a resolution of f(REF)/(k center dot 2M) in a time period of k center dot T-REF. The measured frequency is utilized to calibrate loop bandwidth and VCO frequency. The clock generator is designed in 40 nm CMOS process and operates from 1.2 GHz to 3.6 GHz with 8-phase outputs. The total lock time is less than 3 mu s including calibration and PLL closed-loop locking processes. Operating at 3.2 GHz, the in-band phase noise is better than -99: 4 dBc/Hz and root-mean square ( RMS) jitter integrated from 10 KHz to 100MHz is 2 ps. In the entire operating range, the RMS jitter and reference spur are better than 5.5 ps and -68: 5 dBc/Hz, respectively. The clock generator consumes only 3 mW from 1.1V supply at high-frequency end and 1.6 mW at low-frequency end. The active area is only 0.04 mm(2) including on-chip loop filter and auto-calibration circuits.