Evaluative Comparator Hardware Implementation for State-of-the-Art High Performance Multipliers

The multiplier undoubtedly is one of the most critical digital logic components in computer architecture. To achieve a faster response from a system, digital logic components need to respond faster with negligible error rates. Important factors in the consideration for implementing high performance/speed multipliers are reduction in time delay, power at maximum speed and power delay product. This paper implements and compares high performance multipliers using various algorithms and techniques. It also analyzes the performance of 2, 4 & 8-bit multipliers based on Vedic Algorithm and 4 & 8-bit multipliers based on the Modified Booth Algorithm, and Wallace Tree. The conclusion on the most preferred choice of algorithm across the product dimension is made based on the maximum delay. The multiplier algorithms minimize the delay by reducing the number of partial products. Implementation and analysis of the results have been carried out using Verilog on Xilinx Vivado IDE.