High throughput pipelined hardware implementation of the KECCAK hash function

The cryptographic hash algorithm has been developed by designers with the goal to enhance its performances in terms of frequency, throughput, power consumption and area. The cryptographic hash algorithm is implemented in many embedded systems to ensure security. It is become the default choice to ensure the information integrity in numerous applications. In this paper, we propose a pipelined architecture of the new algorithm SHA-3 (KECCAK). In addition, the proposed KECCAK architecture has been implemented on Xilinx FPGA platform (Virtex-5). Its frequency, efficiency, throughput and area have been compared and discussed. The FPGA implementation results show that the proposed architecture achieves good performance in terms of frequency and throughput.