Verification and Synthesis of Clock-Gated Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems（2019）

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摘要

To reduce dynamic power dissipation in digital circuits, a dependency graph (DG) is derived for a sequential circuit to accomplish verification and synthesis of clock-gated circuits. This is used recursively to derive sufficient conditions for a given bank of flops (flip-flops) to be legally clock gated (disabled.) These conditions are expressed with linear temporal logic (LTL)/past LTL (PLTL) pro...

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关键词

Clocks,Law,Observability,Logic gates,Model checking,Sequential circuits

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