A 0.5 to 1.7 Gbps PI-CDR with a Wide Frequency-Tracking Range.

This paper proposes a continuous-rate clock-data-recovery (CDR) circuit that covers a data rate range of 500 Mbps to 1.7 Gbps. The proposed CDR is based on the phase interpolation principle and implemented in 130 nm CMOS. The design utilizes digital voter and phase control logic instead of analog charge pump and filter, which facilitates migration among different technologies. To avoid the phase interpolator (PI) getting into the nonlinear region, multiple modes are selected to limit the frequency range of the sampling clock within 500 MHz to 1 GHz. A 5 mm(2) test chip is fabricated, where the CDR core occupies 0.359 mm(2) of silicon area. The PI achieves a resolution of 7 bits and a good linearity of 0.9955. The proposed CDR also achieves a BER less than 10(-12) and has a frequency tracking range of +/- 1466 ppm. The power consumed by the proposed CDR is 32.6 mW/Gbps.