A smart-offset analog LDO with 0.3V minimum input voltage and 99.1% current efficiency

In this paper we present the first fully integrated analog LDO (low dropout regulator) for sub-0.5V supply voltages. The LDO can operate from 0.3V-to-1.0V input voltage, and can sustain a load variation of 10mA-to-100mA at 1.0V input and 5mA-to-25mA at 0.3V input. It achieves a peak 99.1% current efficiency for a 100mA load at 0.9V output voltage. In order to realize the gate drive at sub-0.5V supply voltages, we introduce a negative charge pump based adaptive offset before the pass FET which provides gate-source headroom at input operation voltages normally reserved for digital LDOs. The smart-adaptive-negative offset voltage follows a 0.5-0.5×V _DD scheme to accommodate a wide range of input voltages while providing the necessary extra gate drive for the power FET at low inputs. The 32 phase charge pump runs at a frequency of 3GHz with a ripple of ~ 3mV. The prototype was fabricated in TSMC's 65nm GP CMOS.