Towards An Efficient Data Transfer On Mobile Device: A Case Study On Ray-Tracing

In this paper, we propose an efficient ray scheduling algorithm and non-block cache architecture to hiding main-memory access latency targeting real-time ray tracing on mobile device. We first analyze on the impact of memory latency by analyzing the memory access patterns for a ray tracing system and present an energy efficient data transmission method using a dedicated interface between the processor and ray tracing hardware engine. Also we propose a novel ray scheduling method using non-block pipeline feedback and cache architecture. For an evaluation of our approach, we implemented a prototype ray tracing architecture using our approach on an FPGA platform. Our experimental results indicate that our approach shows that shows an average reduction in system memory bandwidth of 48% and average performance improves of 2.4 times.