Analyzing Performance Of Multi-Cores And Applications With Cache-Aware Roofline Model

To satisfy growing computational demands of modern applications, significant enhancements have been introduced in the contemporary processor architectures with the aim to increase their attainable performance, such as increased number of cores, improved capability of memory subsystem and enhancements in the processor pipeline [1]. Therefore, the performance improvements are usually coupled with an increased complexity at the architecture level, which imposes additional challenges when designing, prototyping and optimizing the execution of real-world applications on a given compute platform. Since the application performance depends on multiple factors, e.g., multi-threading, vectorization efficiency and memory accesses, achieving the most efficient execution is not a trivial task, especially when aiming at fully exploiting the capabilities of modern multi-core processors.