Reducing Power, Area, And Delay Of Threshold Logic Gates Considering Non-Integer Weights
2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)(2017)
摘要
This paper shows that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. A novel implementation of non-integer weights is proposed. Experimental results show that the transistor count reduction results in significant reduction in power dissipation and delay.
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关键词
area reduction,delay reduction,threshold logic gates,noninteger weights,threshold logic functions,in CMOS-based current mode logic,reduced transistor count,transistor count reduction,power dissipation reduction
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