A Phase Locking Test Solution For Mems Devices

Physical defects in capacitive MEMS devices can change the nominal device capacitance by a few femtofarads. Detecting such small variations is challenging particularly in the presence of Process, Temperature, and supply Voltage (PVT) variations. A test solution utilizing a phase locking circuit is presented in this paper to minimize the effect of PVT variations on fault detection. A Delay Locked Loop (DLL) is modified to amplify small capacitance variation in order to detect structural faults of capacitive MEMS devices in the time domain. The measurement results on a prototype using 0.18-mu m CMOS indicate that a physical defect changing the nominal capacitance of the device-under-test by 2 fF can be detected using the proposed method.