Efficient VLSI architecture for SAO decoding in 4K Ultra-HD HEVC video codec

Sample Adaptive Offset (SAO) is a new tool added in latest video coding standard (HEVC) to achieve better coding efficiency resulting in higher visual quality. In this paper, we propose efficient and high performance VLSI architecture as well as data transfer scheme for SAO decoder that can work in a pipelined manner achieving 4K (Ultra-HD) resolution at 60 fps in video codec engine. The proposed solution consists of multiple innovative techniques like block based processing, customized scanning order and generic region based transfer scheme to enable very high throughput at low silicon area. The proposed design is coded and simulated for low power 28nm process node. The overall solution achieves performance of 4K resolution at 60 fps at 266 MHz of clock and 0.103 mm ² of logic area after place and route and 127 Kbytes of memory. The proposed design is fully compliant to HEVC video standard handling all corner scenarios.