12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.

Jonathan Chang,Yen-Huei Chen,Wei-Min Chan,Sahil Preet Singh,Hank Cheng,Hidehiro Fujiwara,Jih-Yu Lin,Kao-Cheng Lin,John Hung,Robin Lee,Hung-Jen Liao,Jhon-Jhy Liaw,Quincy Li,Chih-Yung Lin,Mu-Chi Chiang,Shien-Yang Wu

ISSCC（2017）

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关键词

DWL design,FBL design,double WL design,flying BL design,back-end wire RC load,NBL technique,negative bit-line technique,read stability,pass-gate transistor,pull-up transistor,PD transistor,PG transistor,PU transistor,high density SRAM bitcell,length force constrains,quantized channel width,random dopant fluctuation,short-channel effect,capacitance variation,routing resistance,metal interconnection geometry,SOC chip,battery powered mobile device,write-assist circuitry,high-k metal-gate FinFET technology,size 7 nm,storage capacity 256 Mbit

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