A Pipelined Sar Adc Reusing The Comparator As Residue Amplifier

This paper presents a 12-bit two-stage SAR-based pipelined ADC that reuses the comparator from the first-stage SAR to perform residue amplification. This enables residue amplification without increasing the hardware complexity compared to a traditional SAR. The proposed amplifier utilizes positive feedback to achieve a large gain at high speed, which can be difficult to achieve with other dynamic amplifier topologies. Since the comparator is reused for amplification, no additional offset calibration is required to limit the input swing of the amplifier. By utilizing a high resolution in the first stage, the amplifier does not require any nonlinearity calibration. All components in the ADC consume only dynamic power and the architecture uses only scaling-friendly components. The ADC is fabricated in 130-nm CMOS and achieves 63.2 dB SNDR and 75.4 dB SFDR while consuming 0.28 mW at a sampling rate of 10 MS/s. The measured analog power of the prototype is only 11% of the total power which highlights the power efficiency of the proposed residue amplifier. To the authors' knowledge, this work achieves the highest interstage gain of any reported dynamic amplifier.