An Low-Energy 8t Dual-Port Sram For Image Processor With Selective Sourceline Drive Scheme In 28-Nm Fd-Soi Process Technology

This paper presents a low-energy and low-voltage 64-kb 8T dual-port image memory in a 28-nm FD-SOI process technology. Our proposed SRAM adopts the selective sourceline drive (SSD) scheme and the consecutive data write technique for improving active energy efficiency at the low voltage. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology; the test chip exhibits 0.48 V operation and an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operation and 389.6 fJ/cycle in read operation are achieved; these factors are 30% and 26% smaller than those in the 8T dual-port SRAM with the conventional selective sourceline control (SSLC) scheme, respectively.