Enforcing Techniques And Transformation Of C/C Plus Plus Source Code To Heterogeneous Hardware

Besides well-known CPU based architectures, the so-called accelerators (GPU, DSP, FPGA) are about to gain ground in everyday programming and computing tasks. However, programming such computation units is quite different from traditional programming for CPUs, and special skills are required from the developers.In this paper we present techniques and tooling support for the developers in the first step of re-engineering for parallelism in heterogeneous parallel platforms, namely to assure that the code to be offloaded to an accelerator conforms to its specific requirements by identifying the possible violations in the source code, and also by providing automatic code transformations for their elimination.