A Hardware Efficient Multiple-Stream Pipeline Fft Processor For Mimo-Ofdm Systems

In this paper, a hardware efficient design methodology for a configurable-point multiple-stream pipeline FFT processor is presented. We first compared the memory and arithmetic components of different pipeline FFT architectures, and obtained the conclusion that MDF architecture is more hardware efficient than MDC for the overall processor. Then, in order to reduce the computational complexity, a binary-tree representation was adopted to analyze the decomposition algorithm. Consequently, the coefficient multiplications are minimized among all the decomposition probabilities. In addition, an efficient output reorder circuit was designed for the multiple-stream architecture. An 128 2048 point 4-stream FFT processor in LTE system was designed in SMIC 55 nm technology for evaluation. It owns 1.09 mm2 core area with 82.6 mW power consumption at 122.88 MHz clock frequency.