28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications.

Vmin measurements in 28nm FDSOI technology on 128Mb SRAM bitcells from -40 degrees C to 125 degrees C are reported in this paper. Adding the silicon ageing behavior and the process variability, we have developed a complete model and demonstrated end-of-life SRAM Vmin of 0.6V and 0.5V on 20Mb with 0.120 mu m(2) and 0.152 mu m(2) bitcells, respectively. This is the first report of a such extensive SRAM Vmin assessment at the 28nm node. The construction of write limited bitcells, combined with write assist design technique, was found to be the most efficient way to achieve ultra low Vmin in 28nm FDSOI technology. In addition, Vmin retention below 0.4V is demonstrated in 0.120 mu m(2) bitcells, leading to the enablement of ultra-low leakage bitcells with 2pA/cell in retention mode.