A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI

Babak Mohammadi,Oskar Andersson,Joseph Nguyen,Lorenzo Ciampolini,Andreia Cathelin,Joachim Neves Rodrigues

Proceedings of the European Solid-State Circuits Conference（2016）

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摘要

In this study, a 128 kb ultra low voltage (ULV) SRAM, based on a 7T bitcell with one bitline, is presented. Overall energy efficiency is enhanced by optimizations on all abstraction levels, i.e., from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. The minimum operating voltage V _MIN is measured as 240mV and the retention voltage is found at 200mV.

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关键词

single-bitline,7T sense-amplifierless SRAM,FD-SOI,ultralow voltage SRAM,ULV operation,energy efficiency,single-cycle charge-pump,address decoding scheme,static random access memory,frequency 90 MHz,size 28 nm,voltage 300 mV,voltage 240 mV,voltage 200 mV

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