A 0.36v 128kb 6t Sram With Energy-Efficient Dynamic Body-Biasing And Output Data Prediction In 28nm Fdsoi

This paper presents a low-voltage, energy-efficient SRAM designed in a 28nm fully depleted SOI (FDSOI) technology. The SRAM achives a minimum V-dd of 0.36V, while still having the area advantage by using 6T bit-cells. Dynamic forward body-biasing (DFBB) is used to improve the write margin. The proposed implementation of DFBB provides a 4.5 x improvement in energy overhead compared to a conventional implementation. It also helps in reducing the switching energy for half-selected bit-lines. An average energy/bit-access of 52.5fJ has been achieved at 0.45V. Furthermore, by implementing data prediction in the read-path, up to 36% dynamic energy savings can be obtained.