Hierarchical Transactional Memory Protocol for Distributed Mixed-Criticality Embedded Systems

Transactional memories with support for real-time and reliability requirements are a research challenge for the deployment in safety-critical embedded systems. In addition, at present there are no transactional-memory architectures considering hierarchical systems of networked multi-core chips with both on-chip and off-chip networks. The presented work offers a predictable transactional memory solution for hierarchical distributed systems by executing a transactional memory protocol spanning both on-chip and off-chip networks to manage the memory operations of the cores at different multi-core chips. This includes relocating memory pages between the local caches at cores and the external memories while preserving the mixed-criticality requirements of the distributed system. The proposed protocol provides temporal predictability, fault isolation and bounded execution time assurances for safety-critical applications. An automotive use case with a simulation framework serves for the evaluation of the proposed solution.