Flexible scan interface architecture for complex SoCs

Non-standardized scan interface within and across system-on-chips (SoCs) limits test-data reuse for intellectual properties (IPs). To overcome this limitation, we present a flexible and dynamic scan interface architecture that enables reuse of test-data for a given IP across SoCs with different scan pin configurations. The dynamic nature of this architecture also enables variable shift frequencies across different IPs in a given SoC. The architecture decouples the scan pin requirements from the design cycle of the IPs. It also uses bidirectional scan pins to further reduce test cost by using as few as two pins.