A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC.

This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise ...