Total Jitter of Delay-Locked Loops Due to Four Main Jitter Sources.

IEEE Trans. VLSI Syst.(2016)

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摘要
There are four main sources of jitter in delay-locked loops (DLLs). In this paper, DLL’s jitter due to uncertainties in these sources of jitter is calculated. Time domain equations of DLL are introduced, which are the key parameters to obtain a closed-form equation related to jitter of DLL in the presence of noisy phase–frequency detector, charge pump, delay cells, and reference clock. First, DLL’s jitter at the output of each delay cells due to each sources of the jitter will be calculated. Then, the obtained equations are used to calculate the total jitter at the output of all stages. Finally, a DLL is designed in the 0.18- $mu text{m}$ CMOS technology to validate the obtained equations.
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关键词
Delay-locked loop (DLL),jitter,phase noise,phase-locked loop (PLL),phase-locked loop (PLL).
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