A 40-Gb/s serial link transceiver in 28-nm CMOS technology

E.-Hung Chen,Masum Hossain,Brian S. Leibowitz,Reza Navid,Jihong Ren,Chuen-huei Adam Chou,Barry Daly,Marko Aleksic,Bruce Su,Simon Li,Makarand Shirasgaonkar,Fred Heaton,Jared Zerbe,John C. Eble

VLSIC（2014）

引用 60|浏览68

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摘要

A SerDes operating at 40 Gb/s optimized for chip-to-chip communication is presented. Equalization consists of 2-tap feed-forward equalizers (FFE) in both transmitter and receiver, a 3-stage continuous-time linear equalizer (CTLE) and discrete-time equalizers including a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled-FFE in the receiver. The SerDes is realized in 28-nm CMOS technology with 23.2 mW/Gb/s power efficiency at 40 Gb/s.

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关键词

CMOS analogue integrated circuits,decision feedback equalisers,transceivers,17-tap DFE,17-tap decision feedback equalizer,3-stage CTLE,3-stage continuous-time linear equalizer,3-tap sampled-FFE,CMOS technology,SerDes,bit rate 40 Gbit/s,chip-to-chip communication,discrete-time equalizer,feed-forward equalizers,power efficiency,serial link transceiver,size 28 nm,

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