A low-PDP and low-area repeater using passive CTLE for on-chip interconnects

Ming-Shuan Chen,Mau-Chung Frank Chang,Chih-Kong Ken Yang

Symposium on VLSI Circuits-Digest of Papers（2015）

引用 6|浏览22

暂无评分

摘要

This paper presents an improved repeater circuit that preserves the advantages of the inverter repeater and achieves a lower power, delay, and area by applying proper equalization. Designed and measured in 65nm CMOS technology, the proposed repeater achieves 44% lower power-delay product (PDP) while occupies 46% lower area.

查看译文

关键词

low-area repeater,inverter repeater,equalization,CMOS technology,power-delay product,PDP,passive CTLE,on-chip interconnects,size 65 nm

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要