A 6.16gb/S 4.7pj/Bit/Iteration Ldpc Decoder For Ieee 802.11ad Standard In 40nm Lp-Cmos

This paper presents an LDPC decoder employing a column-parallel architecture that enables low-power and high-speed operation suitable for the 802.11ad standard. As compared to the conventional row-parallel architecture, the proposed architecture reduces the required memory size by 60% and also minimizes the number of pipeline stages for high throughput operation. Fabricated in 40nm LP CMOS technology, the prototype achieves high energy efficiency of 4.7pJ/bit/iteration for 6.16Gb/s while supporting all the modulation and coding schemes (MCS0 to MCS12) required for the 802.11ad single-carrier (SC) modulation.