A 28.5-33.5GHz fractional-N PLL using a 3rd order noise shaping time-to-digital converter with 176fs resolution.

This paper presents a 65nm CMOS 28.5GHz-to-33.5GHz mostly digital fractional-N PLL based on a new 3rd order noise-shaping continuous time delta sigma time-to-digital converter (TDC). With a measured time resolution of 176fs, the TDC has the finest measured time resolution in a 1MHz bandwidth of any published TDC, to the best knowledge of the authors. The PLL achieves a normalized phase noise of -213dBc/Hz(2) (at a 100kHz offset) and FoM(Jitter) of -230dB (from 10kHz-to-1MHz). Both the normalized phase noise and FoM(Jitter) are 5dB better than for any published digital integer or digital fractional-N high frequency (>20GHz) PLL.