Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS.
IEEE Journal of Solid-State Circuits(2016)
摘要
A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100 Gb/s communication systems. The model is suitable for ADCs where the analog input bandwidth is of concern and enables a tradeoff between different architectures with respect to the analog input bandwidth, the hold time of the sampled signal, a...
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关键词
Switches,Bandwidth,Capacitors,Jitter,CMOS integrated circuits,Standards
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