An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2015)
摘要
This brief proposes a two-step optimization technique for designing a reconfigurable VLSI architecture of an interpolation filter for multistandard digital up converter (DUC) to reduce the power and area consumption. The proposed technique initially reduces the number of multiplications per input sample and additions per input sample by 83% in comparison with individual implementation of each stan...
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关键词
Finite impulse response filters,Computer architecture,Interpolation,Adders,Hardware,Multiplexing,Very large scale integration
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