Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2016)
摘要
The coarse-grained reconfigurable architectures (CGRAs) are a promising class of architectures with the advantages of high performance and high power efficiency. The compute-intensive parts of an application (e.g., loops) are often mapped onto the CGRA for acceleration. Due to the extra overhead of memory access and the limited communication bandwidth between the processing element (PE) array and ...
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关键词
Routing,Registers,Arrays,Kernel,Cascading style sheets,Topology
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