Implementations Of The Parallel-Sampling Adc Architecture

This chapter describes circuit implementations of the parallel-sampling ADC architecture presented in Chap. 3. The parallel-sampling architecture is applied to two ADC architectures (a pipeline and a time-interleaving SAR ADC architecture), which are suitable for designing high-speed and medium-to-high resolution ADCs, to improve the ADC power efficiency for multi-carrier signals. Section 4.1 describes the architecture and operation of a 200 MS/s 12-b switched-capacitor pipeline ADC with a parallel-sampling first stage, which is suitable for broadband multi-carrier receivers for wireless standards such as LTE-advanced and the emerging generation of Wi-Fi (IEEE802.11ac). A circuit implementation of the parallel-sampling first stage of the pipeline ADC is presented and simulation results are given. Section 4.2 presents the architecture and operation of a 4 GS/s 11 b time-interleaved ADC with a parallel-sampling frontend stage, which targets wideband direct sampling receivers for DOCSIS 3.0 cable modems. Circuit implementation and simulation of the 4 GS/s parallel-sampling frontend stage are given. Due to the complexity of implementing the proposed 4 GS/s ADC on chip, a two-step design approach was adopted. In Sect. 4.3, a prototype IC of an 11 b 1 GS/s ADC with a parallel sampling architecture is presented, which serves as a first step to validate the parallel-sampling ADC concept and the performance of the high-speed parallel-sampling frontend and detection circuits. In future work, the frontend stage of the IC can be interleaved by four times to achieve the aggregate sample rate of 4 GHz of the proposed ADC discussed in Sect. 4.2. Conclusions of this chapter are drawn in Sect. 4.4.